1. Field of the Invention
The present invention generally relates to digital filters and more particularly to an improved interleaved digital filter that eliminates the need for pipeline stages and, in turn, decreases in the number of latches required in the filter, which decreases the power and space required by the filter
2. Description of the Related Art
Finite impulse response digital filters are commonly used to perform arithmetic operations on digital signals (samples) of data. The speed of digital filters is limited by the internal components of the filters. Generally, with full rate design conventional digital filters, one sample can be filtered per cycle. In order to process multiple samples per cycle, an interleaved (half rate) digital filter is utilized.
Interleaved digital filters receive multiple samples (odd and even samples) per cycle and process the odd and even samples in parallel. Therefore, an interleaved digital filter can operate at twice the speed of a full rate design digital filter because the interleaved digital filter processes twice the number of samples per cycle.
However, the disadvantage of interleaved filters is that they include twice the number of multipliers, adders and storage elements when compared to full rate design digital filters. Therefore, the interleaved digital filter are twice as expensive to manufacture and twice as large as a full rate digital filters. However, the interleaved digital filters consume only about the same amount of power as the full rate digital filters because, while the interleaved design requires twice as many elements, the elements operate at half the frequency, which results in an approximately equal power consumption.
FIG. 1 is a schematic diagram of a conventional direct Form 1 interleaved architecture filter. Such a filter is described in greater detail in U.S. Pat. No. 3,665,171, which is incorporated fully herein by reference. More specifically, FIG. 1 illustrate the inputs 10, 11 for the even and odd samples. The samples are multiplied by multipliers h0–h9 after being delayed by the delay elements D. The multiplied samples are then processed through pipelines stages 12 before being added by adders 13. The pipeline stages 12 are necessary to avoid having more than two inputs is supplied to any of the adders 13 during any cycle. The pipeline stages are necessary because there is not enough time to multiply all of the samples and sum them in one cycle. A pipeline stage is used to allow the multiplication to take one cycle and the summation of all the multiplier outputs to take one cycle. Final summation units 14 produce the odd and even filter outputs.
Since all of the multiplier h0–h9 outputs need to be summed at once, pipeline stages 12 are used. The pipeline stages 12 consists of storage elements that hold the outputs of the multipliers for one clock cycle. However, the pipeline stages 12 add an extra cycle of latency and increase the total number of storage elements. Therefore, there is a need to eliminate the pipeline stages 12 from digital filters so that the size of the filter, its associated manufacturing costs, and its power consumption can be reduced.